1. Technical Field
This disclosure relates to processors, and more particularly, to processors that use physical addresses (no virtual addresses).
2. Description of the Related Art
Most modern computer systems use a scheme known as paging in the implementation of memory management. When using paging, a computer loads data into main memory in equally sized blocks known as pages. When paging is used, programs and data may be stored in non-contiguous physical address spaces. This in turn allows for more efficient utilization of the main memory.
During the operation of paged systems, a processor may provide virtual addresses when issuing memory access requests. The virtual addresses may then be translated into physical addresses prior to the actual request being performed. Virtual-to-physical address translations may typically be found in a page table that is stored in the main memory. Some processors may also include a structure known as a translation lookaside buffer (TLB) that can store a limited number of virtual-to-physical address translations that may be more frequently used or more recently accessed. The implementation of these structures in a processor may provide for faster access to a translation, and thus overall faster memory accesses.